Jihun Byun
  byunji@kaist.ac.kr


 Education

  • 2019 ~ present : KAIST, MS candidate, Electrical Engineering
  • 2013 ~ 2019     : Ajou University, BS, Electrical and Computer Engineering



Research





Other Research interests





Publication

  • Journal
  • Selected Conference
  • 1. "Spacer Engineering of Double Gate MOSFET: Performance Study Based on Quantum Transport Simulations" 변지훈이현구, 신민철, 제 27회 반도체 학술대회, 정선, 2020.

  • 2. "Simulation Study of Shape Deformation Effect in Spin-Orbit-Torque Magnetic Random Access Memory," Jihun Byun, Doo Hyung Kang, and Mincheol Shin, Nano Korea 2020, Kintex, Ilsan, Korea, 2020.

  • 3.  "Effect of Shape Deformation by Edge Roughness in Spin-Orbit Torque Magnetoresistive Random-Acess Memory," Jihun Byun, Doo Hyung Kang, and Mincheol Shin, SISPAD, Virtual conference, 2020

  • 4. "Effect of Shape Deformation by Edge Roughness in Spin-Orbit Torque Magnetoresistive Random-Access Memory with Damping Constant Variation," Jihun Byun, Doo Hyung Kang, and Mincheol Shin, MMM, Virtual conference, 2020
  • Patent