Junbeom Seo

 jbseo@kaist.ac.kr


 Education

  • 2017.3. ~             : KAIST, Ph. D Candidate, Electrical Engineering
  • 2016.9. ~ 2017.2  : KAIST, Researcher, Electrical Engineering
  • 2014.3. ~ 2016.8. : KAIST, MS, Electrical Engineering
  • 2008.3. ~ 2014.2. : Kwangwoon University, BS, Electronic Materials Engineering
  • 2005.3. ~ 2008.2. : Hongmyung High School


Research


1. Steep slope devices - Negative Capacitance FETs

  • Conventional MOSFETs have been faced to thermal limit (60mV/dec). To achieve low power devices, a wide variety of the devices has been suggested.
  • NCFETs using ferroelectric materials are one of the candidates to overcome the limit
             - Lower subthreshold swing than 60 mV/dec reducing body factor.
             - High on-current because current flow mechanism of NC-FETs is the same as that of conventional MOSFETs.

     Approach
  • NCFETs are investigated by full-quantum transport simulation (non-equilibrium Green's function) coupled with Landau-Devonshire theory to describe ferroelectric materials.

2. 2-dimensional  material - Black phosphorus




Other Research interests

  • Compound semiconductor
  • Heterojunction


Publication

  • Journal
  1. "Nonorthogonal sp3d5 Tight-Binding Parameterization of Single-Layer Phosphorene under Biaxial Strain and Application to FETs" Jaehyun Lee, Junbeom Seo, Jung Hyun Oh, and Mincheol Shin, Nanotechnology, vol. 27, no. 24, pp. 245202, May 2016
  2. "Analysis of Drain-Induced Barrier Rising in Short-Channel Negative Capacitance FETs and Its Applications", Junbeom Seo, Jaehyun Lee, and Mincheol Shin, Accepted, 2017

  • Selected Conference
  1. "Effects of Strain for Nanowire Schottky Barrier p-MOSFETs", Junbeom Seo, Pooja Srivastave, Jaehyun Lee, Hyo-Eun Jung, Seung chul Kim, Kwang-Ryeol Lee, and Mincheol Shin, ISPSA, Jeju, Korea, 2014 .
  2. "Effects of Ferroelectric Thickness on Negative Capacitance FET Inverters", 서준범, 이재현, 신민철, 제22회 반도체 학술대회, 인천, 2015.
  3. "Multiscale simulation of Schottky barrier tunnel transistors", Mincheol Shin, Pooja Srivastava, Junbeom Seo, Jaehyun Lee, Seungchul Kim, and Kwang-Ryeol Lee, ICCP-9, Singapore, 2015 (invited).
  4. "Comparison of the Temperature Dependent Performances of Negative Capacitance FETs and Conventional MOSFETs", Junbeom Seo, Jaehyun Lee, and Mincheol Shin, AWAD, Jeju Korea, 2015.
  5. "Simulation Study of Double-Gate Tunnel Dielectric-based Tunnel FET", 박상천, 서준범, 정우진, 신민철, 제 23회 반도체 학술대회, 정선, 2016.
  6. "A Study of Performance in Biaxially Strained Single-Layer Black Phosphorus FET", Junbeom Seo, Jaehyun Lee, Jung hyun Oh, and Mincheol Shin, AWAD, Jeju, Korea, 2016
  7. "Efficient TB-NEGF Simulations of Ultra-Thin Body Tunnel FETs", Woo Jin Jeong, Junbeom Seo, and Mincheol Shin, SISPAD, Nuremberg, Germany, 2016.
  8. "First Principles Based NEGF Simulations of Si Nanowire FETs", Mincheol Shin, Woo Jin Jeong, and Junbeom Seo, SISPAD, Nuremberg, Germany, 2016.

  • Patent
  1. 이재현, 서준범, 강두형, 정우진, 신민철, "네거티브 커패시턴스 로직 디바이스, 이를 포함하는 클럭 생성기 및 클럭 생성기의 동작 방법" 
    국가 : 대한민국, 출원번호 : 10-2015-0008700, 출원일 : 2015.1.19.
       2. 이재현, 서준범, 강두형, 정우진, 신민철, "Negative capacitance logic device, clock generator including the same method of            operating clock generator" 
           국가 : 미국, 등록번호 : 9,484,924, 출원일 : 2016.11.1.