Junbeom Seo



  • 2017.3. ~             : KAIST, Ph. D Candidate, School of Electrical Engineering
  • 2016.9. ~ 2017.2  : KAIST, Researcher, School of Electrical Engineering
  • 2014.3. ~ 2016.8. : KAIST, MS, Electrical Engineering
  • 2008.3. ~ 2014.2. : Kwangwoon University, BS, Electronic Materials Engineering


1. Emerging memory devices - Ferroelectric Tunnel Junction

  • In recent years, ferroelectric tunnel junctions (FTJs) have attracted much attention for a promising candidate for next-generation nonvolatile memory devices. The concept of FTJs was first proposed by Esaki et al. in 1971. A typical FTJ consists of two metal electrodes sandwiching a thin ferroelectric film. The resistance switching of FTJ occurs when the tunneling potential barrier in a ferroelectric layer is modulated by the reversal of the electric polarization in the ferroelectric.     
  • DFT simulation
  • Device modeling : Landau-Ginzburg-Devonshire equation + non-equilibrium Green's function
  • Hafnium/Zirconium oxide (HfO2/ZrO2)
  • Perovskite oxide (ABO3)

2. Steep slope devices - Negative Capacitance FETs

  • Conventional MOSFETs have been faced to thermal limit (60mV/dec). To achieve low power devices, a wide variety of devices has been suggested.
  • NCFETs using ferroelectric materials are one of the candidates to overcome the limit
             - Lower subthreshold swing than 60 mV/dec reducing body factor.
             - High on-current because current flow mechanism of NC-FETs is the same as that of conventional MOSFETs.

  • The NCFETs are investigated by full-quantum transport simulation (non-equilibrium Green's function) combining with Landau-Devonshire theory which describes the phase transition of ferroelectric materials.
3. 2-dimensional  material - Black phosphorus

Other Research interests
  • New semiconductor materials and devices


  • Journal
  1. Jaehyun Lee, Junbeom Seo, Jung Hyun Oh, and Mincheol Shin, "Nonorthogonal sp3d5 Tight-Binding Parameterization of Single-Layer Phosphorene under Biaxial Strain and Application to FETs," Nanotechnology, vol. 27, no. 24, pp. 245202, May 2016 (link)
  2. Junbeom Seo, Jaehyun Lee, and Mincheol Shin,"Analysis of Drain-Induced Barrier Rising in Short-Channel Negative Capacitance FETs and Its Applications,"  IEEE Transactions on Electron Devices, vol. 64, no. 4, pp. 1793, April 2017 (link)
  3. Junbeom Seo, Sungwoo Jeong, Mincheol Shin, "The Performance of Uniaxially Strained Phosphorene Tunneling Field-Effect Transistors," IEEE Electron Device Letters, vol. 38, no. 8, pp. 1150 - 1152, Aug. 2017 (link)
  4. Joon-Ho Lee, Woo Jin Jeong, Junbeom Seo, and Mincheol Shin, "Wigner transport simulation of (core gate) silicon-shell nanowire transistors in cylindrical coordinates," Solid State Electronics, vol. 139, pp. 101 - 108, Jan. 2018 (link)
  • Conference
  1. Junbeom Seo, Pooja Srivastave, Jaehyun Lee, Hyo-Eun Jung, Seung chul Kim, Kwang-Ryeol Lee, and Mincheol Shin, "Effects of Strain for Nanowire Schottky Barrier p-MOSFETs," ISPSA, Jeju, Korea, 2014 .
  2. 서준범, 이재현, 신민철, "Effects of Ferroelectric Thickness on Negative Capacitance FET Inverters," 제22회 반도체 학술대회, 인천, 2015.
  3. Mincheol Shin, Pooja Srivastava, Junbeom Seo, Jaehyun Lee, Seungchul Kim, and Kwang-Ryeol Lee, "Multiscale simulation of Schottky barrier tunnel transistors," ICCP-9, Singapore, 2015 (invited).
  4. Junbeom Seo, Jaehyun Lee, and Mincheol Shin, "Comparison of the Temperature Dependent Performances of Negative Capacitance FETs and Conventional MOSFETs," AWAD, Jeju Korea, 2015.
  5. 박상천, 서준범, 정우진, 신민철, "Simulation Study of Double-Gate Tunnel Dielectric-based Tunnel FET," 제 23회 반도체 학술대회, 정선, 2016.
  6. Junbeom Seo, Jaehyun Lee, Jung hyun Oh, and Mincheol Shin, "A Study of Performance in Biaxially Strained Single-Layer Black Phosphorus FET," AWAD, Hakodate, Japan, 2016
  7. Woo Jin Jeong, Junbeom Seo, and Mincheol Shin, "Efficient TB-NEGF Simulations of Ultra-Thin Body Tunnel FETs," SISPAD, Nuremberg, Germany, 2016.
  8. Mincheol Shin, Woo Jin Jeong, and Junbeom Seo, "First Principles-Based NEGF Simulations of Si Nanowire FETs," SISPAD, Nuremberg, Germany, 2016.
  9. 정성우, 서준범, 신민철, "Performance of Black Phosphorus Tunnel FETs under Uniaxial Strain: First-principle Study," 제 24회 반도체 학술대회, 홍천, 2017. (분과우수논문상 수상)
  10.  Junbeom Seo, Sungwoo Jung, and Mincheol Shin, "Effects of Uniaxial Strain on Phosphorene Tunneling Field-Effect Transistors," IWCN, Windermere, United Kingdom, 2017.
  11. Sungwoo Jung, Junbeom Seo, Seonghyun Heo, and Mincheol Shin,  "Performance investigation of uniaxially strained phosphorene n-MOSFETs," SISPAD, Kamakura, Japan, 2017.
  12. 서준범, 김문회, 신민철, "A Simulation Study on Tunneling Electroresistance Effect in Ferroelectric Tunnel Junctions," 제 25회 반도체 학술대회, 정선, 2018.
  13. 김문회, 서준범, 신민철, "New Non-volatile Multi-level Cell Using Epitaxial Strain Effect and Double Ferroelectric Tunnel Junctions," 제 25회 반도체 학술대회, 정선, 2018.
  14. Moonhoi Kim, Junbeom Seo, and Mincheol Shin, "Asymmetrically oxidized interface layer effect of HfO2-based ferroelectric tunnel junctions," Nano Korea 2018, Kintex, Ilsan, Korea, 2018.
  15. Moonhoi Kim, Junbeom Seo, and Mincheol Shin, "Biaxial Strain based Performance Modulation of Negative-Capacitance FETs," SISPAD, Austin, TX, USA, 2018.
  16. Junbeom Seo, Seong Hyeok Jeon, Mincheol Shin, "A Variability Study of Ferroelectric Tunnel Junction," Workshop on Innovative Nanoscale Devices and Systems (WINDS) 2018, Hawaii, USA, 2018.
  17. Hyeongu Lee, Junbeom Seo, and Mincheol Shin, “Quantum Transport Simulations of the Zero Temperature Coefficient in Gate-all-around Nanowire pFETs,”  SISPAD, Udine, Italy, 2019.
  • Patent
  1. 이재현, 서준범, 강두형, 정우진, 신민철, "Negative capacitance logic device, clock generator including the same method of  operating clock generator"  국가 : 미국, 등록번호 : 9,484,924, 등록일 : 2016.11.1.
  2. 이재현, 서준범, 강두형, 정우진, 신민철, "네거티브 커패시턴스 로직 디바이스, 이를 포함하는 클럭 생성기 및 클럭 생성기의 동작 방법" 국가 : 대한민국, 등록번호 : 10-1701145, 등록일 : 2017.1.24.