Yucheol Cho

  yc_cho@kaist.ac.kr


 Education

  • 2018~present: KAIST, Master student, Electrical Engineering
  • 2011~2018: Hongik University, BS, Electronic and Electrical Engineering
  • 2007~2010: Chungnam High School


Research


* First-principles study

1. III-V heterojunction ultra-thin-body tunnel FETs

2. III-V/oxide interface trap




Other Research interests




Publication

  • Journal
  • Selected Conference
  1. "GaSb/InAs Heterojunction-based UTB Tunnel FETs: A first-principles study" 조유철, 장윤희, 신민철, 제 26회 반도체 학술대회, 횡성, 2019.
  2. "Atomistic Simulation of GaSb/InAs Ultra-thin-body Tunnel FETs", Yucheol Cho and Mincheol Shin, Nano Korea 2019, Kintex, Ilsan, Korea, 2019.
  3. “Effect of Trap on Carrier Transport in InAs FET with Al2O3 Oxide: DFT-based NEGF Simulations”,  Mincheol Shin, Yucheol Cho and Seong Hyeok Jeon, SISPAD, Udine, Italy, 2019.
  • Patent