Yucheol Cho

  yc_cho@kaist.ac.kr


 Education

  • 2018~present: KAIST, Master candidate, Electrical Engineering
  • 2011~2018: Hongik University, BS, Electronic and Electrical Engineering
  • 2007~2010: Chungnam High School


Research


1. III-V heterojunction ultra-thin-body tunnel FETs

2. III-V/oxide interface trap




Other Research interests




Publication

  • Journal
  • Selected Conference
  1. "GaSb/InAs Heterojunction-based UTB Tunnel FETs: A first principles study" 조유철, 장윤희, 신민철, 제 26회 반도체 학술대회, 횡성, 2019.
  • Patent