As feature size of conventional planar metal-oxide-semiconductor field-effect transistor (MOSFET) shrinks into the nanometer regime, performance of devices is degraded due to short-channel effects caused by weakened gate control. To overcome this, devices in new structure such as ultra-thin body (UTB), FinFET, nanowire (NW) have emerged. In single nanometer regime, however, semi-classical analysis of such devices is unreliable. Therefore, atomistic level approaches are required. In our laboratory, we develop quantum simulator for devices such as UTB, NW transistors and research by using the results of quantum simulation.
⊙ Advanced MOSFET
A. Silicon nanowire field-effect transistors (Si NWFETs) with multiple gates around the silicon channel that can significantly improve the gate control are therefore considered to be promising candidates for the next generation transistors and have drawn considerable attention recently. In addition to the effective suppression of short channel effects, the SNWFETs with multiple gates show excellent current drive and they are also compatible with conventional CMOS processes.
B. Ultra-thin body field-effect transistor (UTB FET) is said to be a device with very thin body (channel) thickness. Due to the thin-body, UTB FET has high gate control. Moreover, with silicon-on-insulator structure, small leakage current can be achieved. Unlike NWFETs, UTB transistors have already been widely used in semiconductor industry. Double gate type can also be considered to achieve smaller leakage current and higher on-state current. In the case of single nanometer thin body, quantum mechanical effects degrade the device performance, therefore, it is essential to analyze the device performance in quantum picture.
Strain engineering technologies are based on enhancing the transport properties by stressing the channel of the MOFSETs. The advantage of these techniques is that they allow to get higher performance without changing the MOSFET size and architecture dramatically. It can be applied by introducing lattice mismatch, by bending after completion of the device processes, or by rapid thermal process. Strained-nanoscale devices, combining the benefits of enhanced transport characteristics with excellent electrostatic integrity, are seriously considered as a leading solution for future technology nodes.
⊙ Steep Slope device
A. Tunnel field-effect transistor (tFET) operates by the mechanism of band-to-band tunneling. tFET can achieve under 60 mV/dec of sub-threshold swing (SS), so is suitable for low power circuits. Unlike other FETs, its source and drain region are heavily-doped with p+ and n+, respectively. Quantum simulation is necessary to analyze tFET since the main operating mechanism of tFET is tunneling, and one of the issue in terms of tFET is to increase on-state current.
B. Negative capacitance FETs (NCFETs) are one of candidates for steep slope devices. NCFETs are similar to conventional MOFSETs, but the gate insulator in conventional MOFSETs is replaced by ferroelectric. Unlike other steep slope devices, NCFETs can achieve high on current and low sub-threshold swing amplifying gate bias through ferroelectric. Landau equation is used to evaluate ferroelectric and transport of the devices is considered by quantum transport simulation.
⊙ 2D Materials (2DMs)
2DMs have been focused due to their structural and electronic properties. Their weak interlayer interaction can mitigate surface roughness scattering, which is a dominant scattering in UTB FETs.
2DMs that we are currently interested in are summarized below.
Graphene, which is a representative one of 2DMs, has ultra-high mobility. However, its zero bandgap is a big obstacle to gaining high ON/OFF current ratio for transistor operation. Unlike graphene, TMDs and BP have inherent non-zero bandgap, thus, they have great potential for future electronic devices. We analyze properties of the 2DMs in atomistic level, and estimate performance of 2DM-based devices by quantum transport simulation.
⊙ Semiconductor/Insulator Interface
The interest and demand for knowledge of the atomic scale structure of semiconductor/insulator interfaces grows as the size of electronic devices shrinks into the nanoscale dimension. The interface conditions of nanoscale structure become more and more important because low quality interface leads to a loss of gate voltage control for the MOSFETs as well as reduces the device reliability. Intensive research effort has been devoted to investigate interface properties and to search for optimum schemes to improve the interface quality. Recently, understanding on the interface states of III-V/high-k structure has been receiving sustained attention because of its higher performance compared to Si-based devices.
We have performed a theoretical study on atomic structures and electronic properties of interface between channel(semiconductor) and dielectric material(insulator) based on the first-principles density functional theory (DFT). Well-known Si-SiO2 interface structure which shows high thermal stability is analyzed to investigate an ultimate transport performance of the UTB, nanowire MOSFETs. Additionally, we can model the atomic structure of III-V/high-k interface in expectation of high quality interface.
⊙ Schottky Barrier(metal-semiconductor interface)
As gate length will be scaled down to under ~20nm, short channel effects have been significantly considered. In order to suppress short channel effects, body thickness (or junction depth) also will be scaled down to ~6nm. However, resistance in source/drain regions increases because of their thin body. Therefore, contact resistance reduction technology using Schottky junction is proposed.
A key for Schottky junction is Schottky barrier height (SBH). Generally, SBH is determined by Schottky-Mott rule. It predicts the SBH based on the work function of the metal relative to the electron affinity of the semiconductor. However, it was found experimentally that predicted SBH was wrong (Fermi-level pinning effect).
We have performed the first principle calculations (Density functional theory, DFT) to predict the SBH. For doing this job, optimized metal-semiconductor atom structures are necessary. With calculated SBH, we can investigate the performance of Schottky barrier MOSFETs.
Available tools in our lab: SIESTA, openMX
[E. Montes et al., PRB 88, 235411 (2013)]