Junbeom Seo

Junbeom Seo

  • jbseo@kaist.ac.kr

  • jbseo0420@ naver.com


  • 2021.3 ~ present : Samsung Electronics

  • 2017.3. ~ 2021.2 : Ph. D, Electrical Engineering, KAIST

  • 2016.9. ~ 2017.2 : Researcher, Electrical Engineering, KAIST

  • 2014.3. ~ 2016.8. : MS, Electrical Engineering, KAIST

  • 2008.3. ~ 2014.2. : BS, Electronic Materials Engineering, Kwangwoon university


1. Emerging memory devices - Ferroelectric Tunnel Junction

    • In recent years, ferroelectric tunnel junctions (FTJs) have attracted much attention as one of the promising candidates for next-generation nonvolatile memory and neuromorphic devices. The concept of FTJs was proposed by L. Esaki et al. in 1971. A typical FTJ consists of two metal electrodes sandwiching a thin ferroelectric film. The resistance switching of FTJ occurs when the tunnel barrier is modulated by the reversal of the electric polarization in the ferroelectric, leading to different resistance states.


  • DFT simulation: Relaxation of atomistic structures and DFT-NEGF for transport simulation

  • Device modeling (numerical simulation): Landau-Ginzburg-Devonshire equation + NEGF


  • Ferroelectric Hafnium oxide (HfO2)

  • Perovskite oxide (ABO3)

2. Steep slope devices - Negative Capacitance FETs

    • Conventional MOSFETs have been faced with a thermal limit (SS ~ 60mV/dec at 300K). To achieve low power devices, a wide variety of devices has been suggested.

    • NCFETs using ferroelectric materials are one of the candidates to overcome the limit

- Lower subthreshold swing than 60 mV/dec.

- The negative capacitance of ferroelectric layers reduces the body factor (m).

- High ON-state current because the current flow mechanism of NC-FETs is the same as that of conventional MOSFETs.


    • The NCFETs are investigated by full-quantum transport simulation (non-equilibrium Green's function) combining with Landau-Devonshire-Ginzburg theory which describes the phase transition of ferroelectric materials.

3. Two-dimensional material - Black phosphorus

4. New semiconductor materials and devices


  • Journal

    1. Jaehyun Lee, Junbeom Seo, Jung Hyun Oh, and Mincheol Shin, "Nonorthogonal sp3d5 Tight-Binding Parameterization of Single-Layer Phosphorene under Biaxial Strain and Application to FETs," Nanotechnology, vol. 27, no. 24, pp. 245202, May 2016 (link) (IF: 3.440 in 2016)

    2. Junbeom Seo, Jaehyun Lee, and Mincheol Shin," Analysis of Drain-Induced Barrier Rising in Short-Channel Negative Capacitance FETs and Its Applications," IEEE Transactions on Electron Devices, vol. 64, no. 4, pp. 1793, April 2017 (link) (IF: 2.620 in 2017)

    3. Junbeom Seo, Sungwoo Jeong, Mincheol Shin, "The Performance of Uniaxially Strained Phosphorene Tunneling Field-Effect Transistors," IEEE Electron Device Letters, vol. 38, no. 8, pp. 1150 - 1152, Aug. 2017 (link) (IF: 3.433 in 2017)

    4. Joon-Ho Lee, Woo Jin Jeong, Junbeom Seo, and Mincheol Shin, "Wigner transport simulation of (core gate) silicon-shell nanowire transistors in cylindrical coordinates," Solid-State Electronics, vol. 139, pp. 101 - 108, Jan. 2018 (link) (IF: 1.492 in 2018)

    5. Bokyeom Kim, Junbeom Seo, and Mincheol Shin, "Assessing the Performance of Novel Two-Dimensional Materials Transistors: First-Principles-based Approach", IEEE Transactions on Electron Devices, vol. 67, no. 2, pp. 463-468, Feb. 2020 (link) (IF: 2.913 in 2019)

  1. Junbeom Seo and Mincheol Shin, "Atomistic Asymmetric Effect on the Performance of HfO2-based Ferroelectric Tunnel Junctions," Physical Review Applied, vol. 14, 054018, Nov. 2020. (link) (IF: 4.194 in 2019)

  • Domestic conference

  1. 서준범, 이재현, 신민철, "Effects of Ferroelectric Thickness on Negative Capacitance FET Inverters," 제22회 반도체 학술대회, 인천, 2015.

    1. 박상천, 서준범, 정우진, 신민철, "Simulation Study of Double-Gate Tunnel Dielectric-based Tunnel FET," 제 23회 반도체 학술대회, 정선, 2016.

    2. 정성우, 서준범, 신민철, "Performance of Black Phosphorus Tunnel FETs under Uniaxial Strain: First-principle Study," 제 24회 반도체 학술대회, 홍천, 2017. (분과우수논문상 수상)

  2. 서준범, 김문회, 신민철, "A Simulation Study on Tunneling Electroresistance Effect in Ferroelectric Tunnel Junctions," 제 25회 반도체 학술대회, 정선, 2018.

  3. 김문회, 서준범, 신민철, "New Non-volatile Multi-level Cell Using Epitaxial Strain Effect and Double Ferroelectric Tunnel Junctions," 제 25회 반도체 학술대회, 정선, 2018.

  4. 서준범, 신민철, "Tunneling electroresistance Effect Enhanced by Polar Interface in Hafnia-based Ferroelectric Tunnel Junction," 제 27회 반도체 학술대회, 정선, 2020.

  5. 이현구, 서준범, 신민철, "Effects of the Gate Offset on Performance of Double-Gate negative Capacitance Field-Effect Transistors" 제 27회 반도체 학술대회, 정선, 2020. (분과우수논문상 수상)

  • International conference

  1. Junbeom Seo, Pooja Srivastave, Jaehyun Lee, Hyo-Eun Jung, Seung Chul Kim, Kwang-Ryeol Lee, and Mincheol Shin, "Effects of Strain for Nanowire Schottky Barrier p-MOSFETs," ISPSA, Jeju, Korea, 2014.

  2. Mincheol Shin, Pooja Srivastava, Junbeom Seo, Jaehyun Lee, Seungchul Kim, and Kwang-Ryeol Lee, "Multiscale simulation of Schottky barrier tunnel transistors," ICCP-9, Singapore, 2015 (invited).

  3. Junbeom Seo, Jaehyun Lee, and Mincheol Shin, "Comparison of the Temperature-Dependent Performances of Negative Capacitance FETs and Conventional MOSFETs," AWAD, Jeju Korea, 2015.

    1. Junbeom Seo, Jaehyun Lee, Jung hyun Oh, and Mincheol Shin, "A Study of Performance in Biaxially Strained Single-Layer Black Phosphorus FET," AWAD, Hakodate, Japan, 2016

    2. Woo Jin Jeong, Junbeom Seo, and Mincheol Shin, "Efficient TB-NEGF Simulations of Ultra-Thin Body Tunnel FETs," SISPAD, Nuremberg, Germany, 2016.

    3. Mincheol Shin, Woo Jin Jeong, and Junbeom Seo, "First Principles-Based NEGF Simulations of Si Nanowire FETs," SISPAD, Nuremberg, Germany, 2016.

  4. Junbeom Seo, Sungwoo Jung, and Mincheol Shin, "Effects of Uniaxial Strain on Phosphorene Tunneling Field-Effect Transistors," IWCN, Windermere, United Kingdom, 2017.

    1. Sungwoo Jung, Junbeom Seo, Seonghyun Heo, and Mincheol Shin, "Performance investigation of uniaxially strained phosphorene n-MOSFETs," SISPAD, Kamakura, Japan, 2017.

    2. Moonhoi Kim, Junbeom Seo, and Mincheol Shin, "Asymmetrically oxidized interface layer effect of HfO2-based ferroelectric tunnel junctions," Nano Korea 2018, Kintex, Ilsan, Korea, 2018.

    3. Moonhoi Kim, Junbeom Seo, and Mincheol Shin, "Biaxial Strain based Performance Modulation of Negative-Capacitance FETs," SISPAD, Austin, TX, USA, 2018.

  1. Junbeom Seo, Seong Hyeok Jeon, Mincheol Shin, "A Variability Study of Ferroelectric Tunnel Junction," Workshop on Innovative Nanoscale Devices and Systems (WINDS) 2018, Hawaii, USA, 2018.

  2. Hyeongu Lee, Junbeom Seo, and Mincheol Shin, “Quantum Transport Simulations of the Zero Temperature Coefficient in Gate-all-around Nanowire pFETs,” SISPAD, Udine, Italy, 2019.

  3. Junbeom Seo and Mincheol Shin, "First-Principles Study on the Performance of Hafnia-Based Ferroelectric Tunnel Junction with Symmetric Electrodes," ICAE, Jeju, Korea, 2019.

    1. Junbeom Seo and Mincheol Shin, "Effect of Atomic Interface on Tunnel Barrier in Ferroelectric HfO2 Tunnel Junctions," SISPAD, Japan (Virtual conference), 2020

  • Patent

    1. 이재현, 서준범, 강두형, 정우진, 신민철, "Negative capacitance logic device, clock generator including the same method of operating clock generator" 국가 : 미국, 등록번호 : 9,484,924, 등록일 : 2016.11.1.

    2. 이재현, 서준범, 강두형, 정우진, 신민철, "네거티브 커패시턴스 로직 디바이스, 이를 포함하는 클럭 생성기 및 클럭 생성기의 동작 방법" 국가 : 대한민국, 등록번호 : 10-1701145, 등록일 : 2017.1.24.

  1. 임영준, 서준범, 신민철, "터널링 전계 효과 트랜지스터 및 이를 포함하는 반도체 장치" 국가 : 대한민국, 출원번호 : 10-2021-0037091, 출원일 : 2021.03. 23.